首页> 外文OA文献 >Optimized Configurable Architectures for Scalable Soft-Input Soft-Output MIMO Detectors with 256-QAM
【2h】

Optimized Configurable Architectures for Scalable Soft-Input Soft-Output MIMO Detectors with 256-QAM

机译:用于可扩展软输入软输出的优化可配置架构   具有256-Qam的mImO检测器

代理获取
本网站仅为用户提供外文OA文献查询和代理获取服务,本网站没有原文。下单后我们将采用程序或人工为您竭诚获取高质量的原文,但由于OA文献来源多样且变更频繁,仍可能出现获取不到、文献不完整或与标题不符等情况,如果获取不到我们将提供退款服务。请知悉。

摘要

This paper presents an optimized low-complexity and high-throughputmultiple-input multiple-output (MIMO) signal detector core for detectingspatially-multiplexed data streams. The core architecture supports variouslayer configurations up to 4, while achieving near-optimal performance, as wellas configurable modulation constellations up to 256-QAM on each layer. The coreis capable of operating as a soft-input soft-output log-likelihood ratio (LLR)MIMO detector which can be used in the context of iterative detection anddecoding. High area-efficiency is achieved via algorithmic and architecturaloptimizations performed at two levels. First, distance computations and slicingoperations for an optimal 2-layer maximum a posteriori (MAP) MIMO detector areoptimized to eliminate the use of multipliers and reduce the overhead ofslicing in the presence of soft-input LLRs. We show that distances can beeasily computed using elementary addition operations, while optimal slicing isdone via efficient comparisons with soft decision boundaries, resulting in asimple feed-forward pipelined architecture. Second, to support more layers, anefficient channel decomposition scheme is presented that reduces the detectionof multiple layers into multiple 2-layer detection subproblems, which map ontothe 2-layer core with a slight modification using a distance accumulation stageand a post-LLR processing stage. Various architectures are accordinglydeveloped to achieve a desired detection throughput and run-timereconfigurability by time-multiplexing of one or more component cores. Theproposed core is applied as well to design an optimal multi-user MIMO detectorfor LTE. The core occupies an area of 1.58MGE and achieves a throughput of 733Mbps for 256-QAM when synthesized in 90 nm CMOS.
机译:本文提出了一种优化的低复杂度,高吞吐量,多输入多输出(MIMO)信号检测器内核,用于检测空间复用的数据流。核心架构支持高达4的各种层配置,同时实现接近最佳的性能,以及每层高达256-QAM的可配置调制星座图。该核能用作软输入软输出对数似然比(LLR)MIMO检测器,可在迭代检测和解码的情况下使用。通过在两个级别上执行算法和体系结构优化,可以实现较高的区域效率。首先,优化用于最佳2层最大后验(MAP)MIMO检测器的距离计算和切片操作,以消除乘法器的使用并减少在存在软输入LLR的情况下进行切片的开销。我们展示了可以使用基本加法运算轻松地计算出距离,同时通过与软决策边界的有效比较来确定最佳切片,从而实现简单的前馈流水线架构。其次,为了支持更多的层,提出了一种有效的信道分解方案,该方案将对多层的检测减少为多个2层检测子问题,这些问题通过使用距离累积阶段和后LLR处理阶段稍作修改即可映射到2层核心。因此,开发了各种体系结构,以通过一个或多个组件内核的时分复用来实现所需的检测吞吐量和运行时可重新配置性。所提出的核心也被应用于为LTE设计最佳的多用户MIMO检测器。当在90 nm CMOS中合成时,该内核占用1.58MGE的面积,并且对于256-QAM达到733Mbps的吞吐量。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
代理获取

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号